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? semiconductor components industries, llc, 2015 october, 2015 ? rev. 1 1 publication order number: ncp1360/d ncp1360, ncp1365 low power offline constant current & constant voltage primary side pwm current-mode controller with/without high voltage startup current source the ncp1360/65 offers a new solution targeting output power levels from a few watts up to 20 w in a universal?mains flyback application. thanks to a novel method this new controller saves the secondary feedback circuitry (opto?coupler and tl431 reference) while achieving excellent line and load regulation. the ncp1360/65 operates in valley?lockout quasi?resonant peak current mode control mode at nominal load to provide high efficiency. when the secondary?side power starts diminishing, the switching frequency naturally increases until a voltage?controlled oscillator (vco) takes the lead, synchronizing the mosfet turn?on in a drain?source voltage valley. the frequency is thus reduced by stepping into successive valleys until the number 4 is reached. beyond this point, the frequency is linearly decreased in valley?switching mode until a minimum is hit. this technique keeps the output in regulation with the tiniest dummy load. valley lockout during the first four drain?source valleys prevents erratic discrete jumps and provides good efficiency in lighter load situations. features ? primary?side feedback eliminates opto?coupler and tl431 reference ? 5% voltage regulation ? 10% current regulation ? 560 v startup current source ? no frequency clamp, 80 or 110 khz maximum switching frequency options ? quasi?resonant operation with valley switching operation ? fixed peak current & deep frequency foldback @ light load operation. ? external constant voltage feedback adjustment ? cycle by cycle peak current limit ? build?in soft?start ? over & under output voltage protection ? cable drop compensation (none, 150 mv, 300 mv or 450 mv option) ? wide operation v cc r ange (up to 28 v) ? low start?up current (2.5 a typ.) with ncp1360 ? clamped gate?drive output for mosfet ? cs & vs/zcd pin short and open protection ? internal temperature shutdown ? less than 10 mw no?load performance at high line with ncp1365 version ? less than 30 mw no?load performance at high line with ncp1360 version ? these are pb?free devices typical applications ? low power ac?dc adapters for chargers. ? ac?dc usb chargers for cell phones, tablets and cameras tsop?6 case 318g marking diagrams www. onsemi.com (note: microdot may be in either location) 1 xxxayw 1 a = assembly location l = wafer lot y = year w, ww = work week = pb?free package see detailed ordering and shipping information on page 27 o f this data sheet. ordering information soic?7 case 751u xxxxx alywx 1 8
ncp1360, ncp1365 www. onsemi.com 2 1 3 cs v cc 2 drv 4 v s /zcd 6 5 comp gnd figure 1. pin connections (top view) gnd v cc hv v s /zcd comp cs drv 1 2 3 45 6 8 (top view) ncp1360 ncp1365 0 1 2 3 4 5 ncp1365 vs/zcd 1 drv 4 hv 8 comp 2 cs 3 gnd 5 vcc 6 0 vout 0 ac ac figure 2. ncp1365 typical application circuit 0 1 2 3 4 5 0 0 out ac ac ncp1360 zcd 6 comp 5 cs 4 gnd 2 drv 3 vcc 1 figure 3. ncp1360 typical application circuit
ncp1360, ncp1365 www. onsemi.com 3 vcc and logic management of double hiccup s r q uvlo gnd drv uvlo poreset v dd v cc(ovp) fb reset max_ipk reset soft start poreset vs / zcd ocp timer count reset timer v cc(reset) reset double_hiccup_ends comp v cc clamp leb1 blanking cs v ilim ota ss qr multi?mode valley lockout & valley switching & vco management poreset 126% v ref_cv2 latch i cs v dd poreset dblehiccup v uvp ovp_cmp uvp_cmp leb2 v cs(stop) 4 clk counter reset counter note: ovp: over voltage protection uvp: under voltage protection ocp: over current protection scp: short circuit protection cbc: cable compensation t leb1 > t leb2 ocp s r q peak current freeze 1/k comp dblehiccup v cc(ovp) cs pin open (v cs > 2 v) & short (v cs < 50 mv) detection is activated at each startup i cs_en i cs_en scp cs pin fault v ref_cv2 i hv hv s r q s r q uvp dblehiccup v cc v cc(clamp) r lim latch en_uvp en_uvp scp zero crossing & signal sampling cc control sampled v out fb cbc fb_cc fb_cv v ref_cv1 ncp1365 only 4 clk counter v cc(reset) v ref_cc control law & primary peak current control ovp figure 4. functional block diagram: a version ss
ncp1360, ncp1365 www. onsemi.com 4 pin function description pin out ncp1365 pin out ncp1360 name function 1 6 v s /zcd connected to the auxiliary winding; this pin senses the voltage output for the primary regulation and detects the core reset event for the quasi?resonant mode of operation. 2 5 comp this is the error amplifier output. the network connected between this pin and the ground adjusts the regulation loop bandwidth. 3 4 cs this pin monitors the primary peak current. 4 3 drv controller switch driver. 5 2 gnd ground reference. 6 1 v cc this pin is connected to an external auxiliary voltage and supplies the controller. 7 ? nc not connected for creepage distance between high and low voltage pins 8 ? hv connected the high?voltage rail, this pin injects a constant current into the v cc capaci- tor for starting?up the power supply. maximum ratings symbol rating value unit v cc(max) maximum power supply voltage, vcc pin, continuous voltage ?0.3 to 28 v v cc / t maximum slew rate on v cc pin during startup phase +0.4 v/ s v drv(max) i drv(max) maximum driver pin voltage, drv pin, continuous voltage maximum current for drv pin ?0.3, v drv (note 1) ?300, +500 v ma v max i max maximum voltage on low power pins (except pins drv and vcc) current range for low power pins (except pins drv and vcc) ?0.3, 5.5 ?2, +5 v ma v hv high voltage pin voltage ?0.3 to 560 v r j?a thermal resistance junction?to?air 200 c/w t j(max) maximum junction temperature 150 c operating temperature range ?40 to +125 c storage temperature range ?60 to +150 c human body model esd capability per jedec jesd22?a114f 2 kv machine model esd capability (all pins except drv) per jedec jesd22?a115c 200 v charged?device model esd capability per jedec jesd22?c101e 500 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. v drv is the drv clamp voltage v drv(high) when v cc is higher than v drv(high) . v drv is v cc otherwise 2. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78.
ncp1360, ncp1365 www. onsemi.com 5 electrical characteristics: (v cc = 12 v, c drv = 1 nf, for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, max t j = 150 c, unless otherwise noted) characteristics conditions symbol min typ max unit high voltage startup section (ncp1365 only) startup current sourced by v cc pin v hv = 100 v i hv 70 100 150 a leakage current at hv v hv = 400 v i hv_lkg ? 0.1 1 a minimum start?up hv voltage i hv = 95% of i hv @v hv = 100 v, v cc = v cc(on) ? 0.2 v v hv(min) ? 22 25 v supply section and v cc management v cc level at which driving pulses are authorized v cc increasing v cc(on) 16 18 20 v v cc level at which driving pulses are stopped v cc decreasing v cc(off) 6.0 6.5 7.0 v internal latch / logic reset level v cc clamp level v cc(reset) ? 5.6 ? v v cc clamp level (a & c version) activated after latch protection @ i cc = 100 a v cc(clamp) ? 4.2 ? v minimal current into v cc pin that keeps the controller latched (ncp1365, a & c fault mode version) i cc(clamp) ? ? 20 a minimal current into v cc pin that keeps the controller latched (ncp1360, a & c fault mode version) i cc(clamp) ? ? 6 a current?limit resistor in series with the latch scr r lim ? 7 ? k over voltage protection over voltage threshold v cc(ovp) 24 26 28 v start?up supply current, controller disabled or latched (only valid with ncp1360 ) v cc < v cc(on) & v cc increasing from 0 v i cc1 ? 2.5 5.0 a internal ic consumption, steady state f sw = 65 khz, c drv = 1 nf i cc2 ? 1.7 2.5 ma internal ic consumption, frequency foldback mode vco mode, fsw = 1 khz, c drv = 1 nf i cc3 ? 0.8 1.2 ma internal ic consumption when stby mode is activated vco mode, fsw = f vco(min) , v comp = gnd, c drv = 1 nf f vco(min) = 200 hz f vco(min) = 600 hz f vco(min) = 1.2 khz i cc4 ? ? ? 200 220 270 250 tbd* tbd* a current comparator current sense voltage threshold v comp = v comp(max) , v cs increasing v ilim 0.76 0.80 0.84 v cycle by cycle leading edge blanking duration t leb1 250 300 360 ns cycle by cycle current sense propagation delay v cs > (v ilim + 100 mv) to drv turn?off t ilim ? 50 100 ns timer delay before latching in overload condition when cs pin v ilim (note 3) t ocp 50 70 90 ms product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. the timer can be reset if there are 4 drv cycles without overload or short circuit conditions 4. guaranteed by design. * characterization upon request
ncp1360, ncp1365 www. onsemi.com 6 electrical characteristics: (v cc = 12 v, c drv = 1 nf, for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, max t j = 150 c, unless otherwise noted) characteristics unit max typ min symbol conditions current comparator threshold for immediate fault protection activation v cs(stop) 1.08 1.2 1.32 v leading edge blanking duration for v cs(stop) t leb2 ? 120 ? ns maximum peak current level at which vco takes over or frozen peak current v comp < 1.9 v, v cs increasing (~15%v ilim ) v cs(vco) ? 120 ? mv regulation block internal voltage reference for constant current regulation t j = 25 c ?40 c < t j < 125 c v ref_cc 0.98 0.97 1.00 1.00 1.02 1.03 v internal voltage reference for constant voltage regulation t j = 25 c ?40 c < t j < 125 c v ref_cv1 2.450 2.425 2.500 2.500 2.550 2.575 v internal voltage reference for constant voltage regulation when cable compensation is enabled v ref_cv2 ? v ref_cv1 + (cbc/2) ? v error amplifier current capability i ea ? 40 ? a error amplifier gain g ea 150 200 250 s error amplifier output voltage internal offset on comp pin v comp(max) v comp(min) v comp(offset) ? ? ? 4.9 0 1.1 ? ? ? v internal current setpoint division ratio k comp ? 4.0 ? ? valley thresholds transition from 1 st to 2 nd valley transition from 2 nd to 3 rd valley transition from 3 rd to 4 th valley transition from 4 th valley to vco transition from vco to 4 th valley transition from 4 th to 3 rd valley transition from 3 rd to 2 nd valley transition from 2 nd to 1 st valley v comp decreasing v comp decreasing v comp decreasing v comp decreasing v comp increasing v comp increasing v comp increasing v comp increasing v h2d v h3d v h4d v hvcod v hvcoi v h4i v h3i v h2i ? ? ? ? ? ? ? ? 2.50 2.30 2.10 1.90 2.50 2.70 2.90 3.10 ? ? ? ? ? ? ? ? v minimal difference between any two valleys v comp increasing or v comp decreasing v h 176 ? ? mv internal dead time generation for vco mode entering in vco when v comp is decreasing and crosses v hvcod t dt(start) ? 2 ? s internal dead time generation for vco mode leaving vco mode when v comp is increasing and crosses v hvcoi t dt(ends) ? 1 ? s internal dead time generation for vco mode when in vco mode v comp = 1.8 v v comp = 1.3 v v comp = 0.8 v v comp < 0.4 v ? 200 hz option (note 4) v comp < 0.4 v ? 600 hz option (note 4) v comp < 0.4 v ? 1.2 khz option (note 4) t dt ? ? ? ? ? ? 6 25 220 5000 1667 833 ? ? ? ? ? ? s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. the timer can be reset if there are 4 drv cycles without overload or short circuit conditions 4. guaranteed by design. * characterization upon request
ncp1360, ncp1365 www. onsemi.com 7 electrical characteristics: (v cc = 12 v, c drv = 1 nf, for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, max t j = 150 c, unless otherwise noted) characteristics unit max typ min symbol conditions regulation block minimum operating frequency in vco mode v comp = gnd f vco(min) 150 450 0.9 200 600 1.2 250 750 1.5 hz hz khz maximum operating frequency option option f max ? 75 103 no clamp 80 110 ? 85 117 n/a khz khz demagnetization input ? zero voltage detection circuit and voltage sense v zcd threshold voltage v zcd decreasing v zcd(th) 25 45 65 mv v zcd hysteresis v zcd increasing v zcd(hys) 15 30 45 mv threshold voltage for output short circuit or aux. winding short circuit detection after t blank_pd if v zcd < v zcd(short) latched v zcd(short) 30 50 70 mv propagation delay from valley detection to drv high v zcd decreasing from 4 v to 0 v t dem ? ? 170 ns delay after on?time that the v s /zcd is still pulled to ground (note 4) t short_zcd ? 0.7 ? s blanking delay after on?time (v s /zcd pin is disconnected from the internal circuitry) t blank_zcd 1.2 1.5 1.8 s timeout after last demagnetization transition timeout while in soft?start timeout after soft?start complete t outss t out 36 4.5 44 5.5 52 6.5 s input leakage current v cc > v cc(on) v zcd = 4 v, drv is low i zcd ? ? 0.1 a drive output ? gate drive drive resistance drv sink drv source r snk r src ? ? 7 12 ? ? rise time c drv = 1 nf, from 10% to 90% t r ? 45 80 ns fall time c drv = 1 nf, from 90% to 10% t f ? 30 60 ns drv low voltage v cc = v cc(off) + 0.2 v, c drv = 220 pf, r drv = 33 k v drv(low) 6.0 ? ? v drv high voltage v cc = v cc(ovp) ?0.2 v , c drv = 220 pf, r drv = 33 k v drv(high) ? ? 13.0 v soft start internal fixed soft start duration current sense peak current rising from 0.2 v to 0.8 v t ss 3 4 5 ms fault protection thermal shutdown device switching (f sw 65 khz) (note 4) t shtdn ? 150 ? c thermal shutdown hysteresis device switching (f sw 65 khz) (note 4) t shtdn(hys) ? 40 ? c number of drive cycle before latch confirmation v comp = v comp(max) , v cs > v cs(stop) or internal sampled v out > v ovp t latch_count ? 4 ? ? product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. the timer can be reset if there are 4 drv cycles without overload or short circuit conditions 4. guaranteed by design. * characterization upon request
ncp1360, ncp1365 www. onsemi.com 8 electrical characteristics: (v cc = 12 v, c drv = 1 nf, for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, max t j = 150 c, unless otherwise noted) characteristics unit max typ min symbol conditions fault protection fault level detection for ovp latched (v cc = v cc(clamp) with low consumption mode) internal sampled v out increasing v ovp = v ref_cv2 +26% v ovp 2.95 3.15 3.35 v fault level detection for uvp double hiccup autorecovery (uvp detection is disabled during t en_uvp ) internal sampled v out decreasing v uvp 1.4 1.5 1.6 v blanking time for uvp detection starting at the beginning of the soft start t en_uvp ? 37 ? ms pull?up current source on cs pin for open or short circuit detection when v cs > v cs_min i cs ? 55 ? a cs pin open detection cs pin open v cs(open) 0.8 ? ? v cs pin short detection v cs_min ? 50 70 mv cs pin short detection timer (note 4) t cs_short ? 3 ? s cable drop compensation offset applied on v ref_cv1 at the maximum constant current option a option b option c option d cbc ? ? ? ? none 150 300 450 ? ? ? ? mv product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. the timer can be reset if there are 4 drv cycles without overload or short circuit conditions 4. guaranteed by design. * characterization upon request
ncp1360, ncp1365 www. onsemi.com 9 fault mode states table whatever the version event timer protection next device status release to normal operation mode overcurrent v cs > v ilim ocp timer double hiccup ? resume to normal operation: if 4 pulses from fb reset & then reset timer ? resume operation after double hiccup winding short v cs > v cs(stop) immediate 4 consecutive pulses with v cs > v cs(stop) before latching v cc is decreasing to v cc(clamp) and waiting for unplug from line v cc < v cc(reset) cs pin fault: short & open immediate double hiccup resume operation after double hiccup low supply v cc < v cc(off) 10 s timer double hiccup resume operation after double hiccup internal tsd 10 s timer double hiccup resume operation after double hiccup & t < (t shtdn ? t shtdn(hyst) ) zcd short v zcd < v zcd(short) after t blank_pd time immediate double hiccup resume operation after double hiccup (v cc(on) < v cc < v cc(reset) ) fault mode states table according the controller versions event a version b version c version high supply v cc > v cc(ovp) latched_timer autorecovery latched_timer internal v out ovp: v out > 126% v ref_cv2 latched_4clk autorecovery latched_4clk internal v out uvp: v out < 60% v ref_cv2 , when v out is decreasing only autorecovery autorecovery latched_timer fault type mode definition fault mode timer protection next device status release to normal operation mode latched_timer 10 s timer latched v cc is decreasing to v cc(clamp) and waiting for un- plug from line v cc < v cc(reset) latched_4clk immediate 4 consecutive pulses with v cs > 126% v ref_cv2 before latching v cc is decreasing to v cc(clamp) and waiting for un- plug from line v cc < v cc(reset) autorecovery immediate resume operation after double hiccup resume operation after double hiccup (v cc(on) < v cc < v cc(reset) )
ncp1360, ncp1365 www. onsemi.com 10 characterization curves 20 19.5 19 18.5 18 17.5 17 16.5 16 ?50 ?25 0 25 50 75 100 125 150 figure 5. v cc startup threshold versus temperature t j , temperature ( c) v cc(on) (v) 7.0 ?50 ?25 0 25 50 75 100 125 150 figure 6. v cc minimum operating versus temperature t j , temperature ( c) v cc(off) (v) 6.9 6.8 6.7 6.6 6.5 6.4 6.3 6.2 6.1 6.0 6.6 ?50 ?25 0 25 50 75 100 125 150 figure 7. v cc(reset) versus temperature t j , temperature ( c) v cc(reset) (v) 6.4 6.2 6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 28.0 ?50 ?25 0 25 50 75 100 125 150 figure 8. v cc(ovp) versus temperature t j , temperature ( c) v cc(ovp) (v) 27.5 27.0 26.5 26.0 25.5 25.0 24.5 24.0 160 ?50 ?25 0 25 50 75 100 125 150 figure 9. startup current source versus temperature t j , temperature ( c) i hv ( a) 150 140 130 120 110 100 90 80 70 60 1.0 ?50 ?25 0 25 50 75 100 125 150 figure 10. hv pin leakage versus temperature t j , temperature ( c) i hv_lkg ( a) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
ncp1360, ncp1365 www. onsemi.com 11 characterization curves 24 ?50 ?25 0 25 50 75 100 125 150 figure 11. minimum voltage for hv startup current source versus temperature t j , temperature ( c) v hv(min) (v) 2.4 ?50 ?25 0 25 50 75 100 125 150 figure 12. i cc2 versus temperature t j , temperature ( c) i cc2 (ma) 1.00 ?50 ?25 0 25 50 75 100 125 150 figure 13. i cc3 versus temperature t j , temperature ( c) i cc3 (ma) 0.25 ?50 ?25 0 25 50 75 100 125 150 figure 14. standby current consumption (200 hz option) versus temperature t j , temperature ( c) i cc4 (ma) 0.84 ?50 ?25 0 25 50 75 100 125 150 figure 15. max peak current limit versus temperature t j , temperature ( c) v ilim (v) 1.32 ?50 ?25 0 25 50 75 100 125 150 figure 16. second peak current limit for fault protection versus temperature t j , temperature ( c) v cs(stop) (v) 22 20 18 16 14 12 10 2.0 2.0 1.8 1.6 1.4 1.2 1.0 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.24 0.23 0.22 0.21 0.20 0.19 0.18 0.17 0.16 0.15 0.14 0.83 0.82 0.81 0.80 0.79 0.78 0.77 0.76 1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16 1.14 1.10 1.08
ncp1360, ncp1365 www. onsemi.com 12 characterization curves 1.02 ?50 ?25 0 25 50 75 100 125 150 figure 17. internal voltage reference for constant current regulation versus temperature t j , temperature ( c) v ref_cc (v) 2.60 ?50 ?25 0 25 50 75 100 125 150 figure 18. internal voltage reference for constant voltage regulation versus temperature t j , temperature ( c) v ref_cv1 (v) 3.40 ?50 ?25 0 25 50 75 100 125 150 figure 19. output over voltage level versus temperature t j , temperature ( c) v ovp (v) 1.60 ?50 ?25 0 25 50 75 100 125 150 figure 20. output under voltage level versus temperature t j , temperature ( c) v uvp (v) 360 ?50 ?25 0 25 50 75 100 125 150 figure 21. cycle?by?cycle leading edge blanking duration versus temperature t j , temperature ( c) t leb1 (ns) 180 ?50 ?25 0 25 50 75 100 125 150 figure 22. leading edge blanking duration for v cs(stop) level versus temperature t j , temperature ( c) t leb2 (ns) 1.01 1.00 0.99 0.98 2.58 2.56 2.54 2.52 2.50 2.48 2.46 2.44 2.42 2.40 3.35 3.30 3.25 3.20 3.15 3.10 3.05 3.00 2.95 2.90 1.58 1.56 1.54 1.52 1.50 1.48 1.46 1.44 1.42 1.40 340 320 300 280 260 240 160 140 120 100 80 60
ncp1360, ncp1365 www. onsemi.com 13 characterization curves 100 ?50 ?25 0 25 50 75 100 125 150 figure 23. cycle?by?cycle current sense propagation delay versus temperature t j , temperature ( c) t ilim (ns) 52 ?50 ?25 0 25 50 75 100 125 150 figure 24. timeout after last demagnetization transition in soft?start versus temperature t j , temperature ( c) t outss ( s) 6.5 ?50 ?25 0 25 50 75 100 125 150 figure 25. timeout after last demagnetization transition versus temperature t j , temperature ( c) t out ( s) 95 ?50 ?25 0 25 50 75 100 125 150 figure 26. timer delay before latching in overload condition versus temperature t j , temperature ( c) t ocp (ms) 65 ?50 ?25 0 25 50 75 100 125 150 figure 27. zero voltage detection threshold voltage versus temperature t j , temperature ( c) v zcd(th) (mv) 45 ?50 ?25 0 25 50 75 100 125 150 figure 28. zero voltage detection hysteresis versus temperature t j , temperature ( c) v zcd(hys) (mv) 80 60 40 20 0 50 48 46 44 42 40 38 36 6.3 6.1 5.9 5.7 5.5 5.3 5.1 4.9 4.7 4.5 90 85 80 75 70 65 60 55 50 45 60 55 50 45 40 35 30 25 40 35 30 25 20 15
ncp1360, ncp1365 www. onsemi.com 14 characterization curves 1.8 ?50 ?25 0 25 50 75 100 125 150 figure 29. blanking delay for zcd detection versus temperature t j , temperature ( c) t blank_zcd ( s) 8.0 ?50 ?25 0 25 50 75 100 125 150 figure 30. v drv(low) versus temperature t j , temperature ( c) v drv(low) (v) 13.0 ?50 ?25 0 25 50 75 100 125 150 figure 31. v drv(high) versus temperature t j , temperature ( c) v drv(high) (v) 80 ?50 ?25 0 25 50 75 100 125 150 figure 32. gate drive rise time versus temperature t j , temperature ( c) t r (ns) 60 ?50 ?25 0 25 50 75 100 125 150 figure 33. gate drive fall time versus temperature t j , temperature ( c) t f (ns) 250 ?50 ?25 0 25 50 75 100 125 150 figure 34. error amplifier gain versus temperature t j , temperature ( c) g ea ( s) 1.7 1.6 1.5 1.4 1.3 1.2 7.8 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 12.5 12.0 11.5 11.0 10.5 10.0 70 60 50 40 30 20 10 0 240 230 220 210 200 190 180 170 160 150 50 40 30 20 10 0
ncp1360, ncp1365 www. onsemi.com 15 characterization curves 50 ?50 ?25 0 25 50 75 100 125 150 figure 35. error amplifier max. source capability versus temperature t j , temperature ( c) i ea ( a) ?30 ?50 ?25 0 25 50 75 100 125 150 figure 36. error amplifier max. sink capability versus temperature t j , temperature ( c) i ea ( a) 130 ?50 ?25 0 25 50 75 100 125 150 figure 37. minimum or frozen peak current on cs pin versus temperature t j , temperature ( c) v cs(vco) (mv) 70 ?50 ?25 0 25 50 75 100 125 150 figure 38. threshold level for detecting output or aux. winding short versus temperature t j , temperature ( c) v zcd(short) (mv) 40 ?50 ?25 0 25 50 75 100 125 150 figure 39. startup blanking time for uvp detection versus temperature t j , temperature ( c) t en_uvp (ms) 75 ?50 ?25 0 25 50 75 100 125 150 figure 40. pull?up current source for detecting open or short on cs pin versus temperature t j , temperature ( c) i cs ( a) 48 46 44 42 40 38 36 34 32 30 ?32 ?34 ?36 ?38 ?40 ?42 ?44 ?46 ?48 ?50 125 120 115 110 105 100 65 60 55 50 45 40 35 30 39 38 37 36 35 34 33 32 31 30 70 65 60 55 50 45 40 35 30 25
ncp1360, ncp1365 www. onsemi.com 16 characterization curves 75 ?50 ?25 0 25 50 75 100 125 150 figure 41. cs pin short detection threshold versus temperature t j , temperature ( c) v cs_min (mv) 1.20 ?50 ?25 0 25 50 75 100 125 150 figure 42. cs pin open detection threshold versus temperature t j , temperature ( c) v cs(open) (v) 70 65 60 55 50 45 40 35 30 25 1.10 1.00 0.90 0.80 0.70 0.60
ncp1360, ncp1365 www. onsemi.com 17 application information the ncp1365/60 is a flyback power supply controller providing a means to implement primary side constant?voltage and constant?current regulation. this technique does not need a secondary side feedback circuitry, associated bias current and an opto?coupler. ncp1365/60 implements a current?mode architecture operating in quasi?resonant mode. the controller prevents valley?jumping instability and steadily locks out in a selected valley as the power demand goes down. as long as the controller is able to detect a valley, the new cycle or the following drive remains in a valley. due to a dedicated valley detection circuitry operating at any line and load conditions, the power supply efficiency will always be optimized. in order to prevent any high switching frequency two frequency clamp options are available. ? quasi?resonance current?mode operation : implementing quasi?resonance operation in peak current?mode control optimizes the efficiency by switching in the valley of the mosfet drain?source voltage. thanks to a proprietary circuitry, the controller locks?out in a selected valley and remains locked until the input voltage significantly changes. only the four first valleys could be locked out. when the load current diminishes, valley switching mode of operation is kept but without valley lock?out. valley?switching operation across the entire input/output conditions brings efficiency improvement and lets the designer build higher?density converters. ? frequency clamp : as the frequency is not fixed and dependent on the line, load and transformer specifications, it is important to prevent switching frequency runaway for applications requiring maximum switching frequencies up to 90 khz or 130 khz. two frequency clamp options at 80 khz or 110 khz are available for this purpose. in case frequency clamp is not needed, a specific version of the 1365/60 exists in which the clamp is deactivated. ? primary side constant current regulation : battery charging applications request constant current regulation. ncp1360/65 controls and regulates the output current at a constant level regardless of the input and output voltage conditions. this function offers tight over power protection by estimating and limiting the maximum output current from the primary side, without any particular sensor. ? primary side constant voltage regulation : by monitoring the auxiliary winding voltage on the primary side, it is possible to determine the end of the transformer demagnetization in order to indirectly measure the output voltage. the end of the auxiliary winding demagnetization corresponds to that of the secondary winding affected by the transformer turns ratio. this auxiliary voltage value captured at this moment will be used to build the primary?side peak current setpoint in order to control the output voltage. v out i out cv mode cc mode 0 v nom i nom figure 43. constant?voltage & constant?current mode ? soft?start : 4 ms internal fixed soft start guarantees a peak current starting from zero to its nominal value with smooth transition in order to prevent any overstress on the power components at each startup. ? cycle?by?cycle peak curr ent limit : if the max peak current reaches the v ilim level, the over current protection timer is enabled and starts counting. if the overload lasts t ocp delay, then the fault is latched and the controller stops immediately driving the power mosfet. the controller enters in a double hiccup mode before autorecovering with a new startup cycle. ? v cc over voltage protection : if the v cc voltage reaches the v cc(ovp) threshold the controller enters in latch mode. thus it stops driving pulse on drv pin: ? a & c version ? (latched v cc ( ovp ) ) : v cc capacitor is internally discharged to the v cc ( clamp ) level with a very low power consumption: the controller is completely disabled. resuming operation is possible by unplugging the line in order to releasing the internal v cc thyristor with a v cc current lower than the i cc ( clamp ) . ? b version ? (autorecovery) : it enters in double hiccup mode before resuming operation. ? winding short?cir cuit protection : an additional comparator senses the cs signal and stops the controller if v cs reaches v ilim +50% (after a reduced leb: t leb2 ). short circuit protection is enabled only if 4 consecutive pulses reach scp level. this small counter prevents any false triggering of short circuit protection during surge test for instance. this fault is latched and operations will be resumed like in a case of v cc over voltage protection.
ncp1360, ncp1365 www. onsemi.com 18 ? v out over voltage protection : if the internally?built output voltage becomes higher than v ovp level ( v ref_cv1 + 26%) a fault is detected. ? a & c version : this fault is latched and operations are resumed like in the v cc over voltage protection case. ? b version : the part enters in double hiccup mode before resuming operations. ? v out under voltage protection : after each circuit power on sequence, v out uvp detection is enabled only after the startup timer t en_uvp . this timer ensures that the power supply is able to fuel the output capacitor before checking the output voltage in on target. after this startup blanking time, uvp detection is enabled and monitors the output voltage level. when the power supply is running in constant?current mode and when the output voltage falls below v uvp level, the controller stops sending drive pulses and enters a double hiccup mode before resuming operations (a & b version), or latches off (c version). ? v s /zcd pin short protection : at the beginning of each off?time period, the v s /zcd pin is tested to check whether it is shorted or left open. in case a fault is detected, the controller enters in a double hiccup mode before resuming operations. ? temperature shutdown : if the junction temperature reaches the t shtdn level, the controller stop driving the power mosfet until the junction temperature decreases by t shtdn(hys) , then the operation is resumed after a double hiccup mode. startup operation the high?voltage startup current source is connected to the bulk capacitor via the hv pin, it charges the v cc capacitor. during startup phase, it delivers 100 a to fuel the v cc capacitor. when v cc pin reaches v cc ( on ) level, the ncp1360/65 is enabled. before sending the first drive pulse to the power mosfet, the cs pin has been tested for an open or shorted situation. if cs pin is properly wired, then the controller sends the first drive pulse to the power mosfet. after sending these first pulses, the controller checks the correct vs/zcd pin wiring. considering the vs/zcd pin properly wired, the controller engages a softstart sequence. the softstart sequence controls the max peak current from the minimal frozen primary peak current ( v cs(vco) = 120 mv: 15% of v ilim ) to the nominal pulse width by smoothly increasing the level. figure 44 illustrates a standard connection of the hv pin to the bulk capacitor. if the controller is in a latched fault mode (ex v cc_ovp has been detected), the power supply will resume the operation after unplugging the converter from the ac line outlet. due the extremely low controller consumption in latched mode, the release of the latch could be very long. the unplug duration for releasing the latch will be dependent on the bulk capacitor size. l n 8 5 drv gnd vs/zcd hv comp 6 vcc cs v bulk r hv c vcc v aux 1 2 4 2 figure 44. hv startup connection to the bulk capacitor the following calculation illustrates the time needed for releasing the latch state: t unplug c bulk v in_ac 2 i hv (eq. 1) for the following typical application with a 10 f bulk capacitor and a wide mains input range, in the worst case the power supply needs to be unplug at least for 38 seconds @ 265 v ac and 12 seconds @ 85 vac. it is important to note that the previous recommendation is no longer valid with the b version, as all the faults are set to autorecovery mode only. protecting the controller against negative spikes as with any controller built upon a cmos technology, it is the designer?s duty to avoid the presence of negative spikes on sensitive pins. negative injection has the bad habit to forward?bias the controller substrate and can induce erratic behaviors. sometimes, the injection can be so strong that internal parasitic scrs are triggered and latch the controller. the hv pin can be the problem in certain circumstances. during the turn?off sequence, e.g. when the user unplugs the power supply, the controller is still fed by its v cc capacitor and keeps activating the mosfet on and
ncp1360, ncp1365 www. onsemi.com 19 off with a peak current limited by r sense . unfortunately, if the quality factor q of the resonating network formed by l p and c bulk is high (e.g. the mosfet r ds(on) + r sense are small), conditions are met to make the circuit resonate and a negative ringing can potentially appear at the hv pin. simple and inexpensive cures exist to prevent the internal parasitic scr activation. one of them consist of inserting a resistor in series with the hv pin to keep the negative current at the lowest when the bulk swings negative (figure 44). another option (figure 45) consists of connecting the hv pin directly to the line or neutral input via a high?voltage diode. this configuration offers the benefits to release a latch state immediately after unplugging the power supply from the mains outlet. there is no delay for resetting the controller as there no capacitor keeps the hv bias. r hv resistor value must be sized as follow in order to guarantee a correct behavior of the hv startup in the worst case conditions: r hv v in,ac_min 2 v hv(min)_max i hv_max (eq. 2) where: ? v in,ac_min is minimal input voltage, for example 85 v ac for universal input mains. ? v hv(min)_max is the worst case of the minimal input voltage needed for the hv startup current source (25 v?max). ? i hv_max is the maximum current delivered by the hv startup current source (150 a?max) with this typical example r hv 85 2 25 150 633 k , then any value below this one will be ok. l n 1 2 4 8 5 drv gnd vs/zcd hv comp 6 vcc 2cs v bulk v aux c vcc figure 45. recommended hv startup connection for fast release after a latched fault primary side regulation: constant current operation figure 46 portrays idealized primary and secondary transformer currents of a flyback converter operating in discontinuous conduction mode (dcm). figure 46. primary and secondary transformer current waveforms i p (t) i s (t), i out i out = < i s (t) > , , ppk spk i ps i n = , p i pk t demag t sw time time t on
ncp1360, ncp1365 www. onsemi.com 20 when the primary power mosfet is turned on, the primary current is illustrated by the green curve of figure 46. when the power mosfet is turned off the primary side current drops to zero and the current into the secondary winding immediately rises to its peak value equal to the primary peak current divided by the primary to secondary turns ratio. this is an ideal situation in which the leakage inductance action is neglected. the output current delivered to the load is equal to the average value of the secondary winding current, thus we can write: i out i sec ( t ) i p,pk 2n ps t demag t sw (eq. 3) where: ? t sw is the switching period ? t demag is the demagnetizing time of the transformer ? n ps is the secondary to primary turns ratio, where n p and n s are respectively the transformer primary and secondary turns: n ps n s n p (eq. 4) ? i p,pk is the magnetizing peak current sensed across the sense resistor on cs pin: i p,pk v cs r sense (eq. 5) internal constant current regulation block is building the constant current feedback information as follow: v fb_cc v ref_cc t sw t demag (eq. 6) as the controller monitors the primary peak current via the sense resistor and due to the internal current setpoint divider ( k comp ) between the cs pin and the internal feedback information, the output current could be written as follow: i out v ref_cc 8n ps r sense (eq. 7) the output current value is set by choosing the sense resistor value: r sense v ref_cc 8n ps i out (eq. 8) primary side regulation: constant voltage operation in primary side constant voltage regulation, the output voltage is sensed via the auxiliary winding. during the on?time period, the energy is stored in the transformer gap. during the off?time this energy stored in the transformer is delivered to the secondary and auxiliary windings. as illustrated by figure 47, when the transformer energy is delivered to the secondary, the auxiliary voltage sums the output voltage scaled by the auxiliary and secondary turns ratios and the secondary forward diode voltage. this secondary forward diode voltage could be split in two elements: the first part is the forward voltage of the diode ( v f ), and the second is related to the dynamic resistance of the diode multiplied by secondary current ( r d i s (t) ). where this second term will be dependant of the load and line conditions. pa in ps n v n ? 0v v aux (t) time t demag t sw time , , ppk spk ps i i n = , ppk i time t on i p (t) i s (t), i out i out = < i s v out n pa n ps v f ( i sec ) figure 47. typical idealized waveforms of a flyback transformer in dcm (t) > v out n pa n ps
ncp1360, ncp1365 www. onsemi.com 21 to reach an accurate primary?side constant?voltage regulation, the controller detects the end of the demagnetization time and precisely samples output voltage level seen on the auxiliary winding. as this moment coincides with the secondary?side current equal to zero, the diode forward voltage drop becomes independent from the loading conditions. thus when the secondary current i s ( t ) reaches zero ampere, the auxiliary is sensed: v aux v out n pa n ps (eq. 9) where: n pa is the auxiliary to primary turns ratio, where n p & n a are respectively the primary and auxiliary turns: n pa n a n p (eq. 10) figure 48 illustrates how the constant voltage feedback has been built. the auxiliary winding voltage must be scaled down via the resistor divider to v ref_cv1 level before building the constant voltage feedback error. v ref_cv1 r s2 r s1 r s2 v aux (eq. 11) by inserting equation 9 into equation 11 we obtain the following equation: v ref_cv1 r s2 r s1 r s2 n pa n ps v out (eq. 12) once the sampled v out is applied to the negative input terminal of the operational transconductance amplifier ( ota ) and compared to the internal voltage reference an adequate voltage feedback is built. the ota output being pinned out, it is possible to compensate the converter and adjust step load response to what the project requires. vs / zcd comp ota zero crossing & signal sampling sampled v out fb_cv auxiliary r s1 r s2 v ref_cv1 r1 c1 c2 t short_zcd figure 48. constant voltage feedback arrangement t blank_zcd when the power mosfet is released at the end of the on time, because of the transformer leakage inductance and the drain lumped capacitance some voltage ringing appears on the drain node. these voltage ringings are also visible on the auxiliary winding and could cheat the controller detection circuits. to avoid false detection operations, two protecting circuits have been implemented on the v s /zcd pin (see figure 49): 1. an internal switch grounds the v s /zcd pin during t on +t short_zcd in order to protect the pin from negative voltage. 2. in order to prevent any misdetection from the zero crossing block an internal switch disconnects v s /zcd pin until t blank_zcd time (1.5 s typ.) ends.
ncp1360, ncp1365 www. onsemi.com 22 figure 49. v s /zcd pin waveforms constant?current and constant?voltage overall regulation: as already presented in the two previous paragraphs, the controller integrates two different feedback loops: the first one deals with the constant?current regulation scheme while the second one builds the constant?voltage regulation. one of the two feedback paths sets the primary peak current into the transformer. during startup phase, however, the peak current is controlled by the soft?start. zero current detection the ncp1365 integrates a quasi?resonant (qr) flyback controller. the power switch turn?off of a qr converter is determined by the peak current whose value depends on the feedback loop. the switch restart event is determined by the transformer demagnetization end. the demagnetization end is detected by monitoring the transformer auxiliary winding voltage. turning on the power switch once the transformer is demagnetized (or reset) reduces turn?on switching losses. once the transformer is demagnetized, the drain voltage starts ringing at a frequency determined by the transformer magnetizing inductance and the drain lumped capacitance, eventually settling at the input voltage value. a qr controller takes advantage of the drain voltage ringing and turns on the power switch at the drain voltage minimum or ?valley? to reduce turn?on switching losses and electromagnetic interference (emi). as sketched by figure 50, a valley is detected once the zcd pin voltage falls below the qr flyback demagnetization threshold, v zcd(th) , typically 45 mv. the controller will switch once the valley is detected or increment the valley counter depending on fb voltage. r s1 r s2 zcd timeout (t outss or t out ) qr multi?mode valley lockout & valley switching & vco management blanking t blank_zcd s r q drv (internal) v zcd(th) figure 50. valley lockout detection circuitry internal schematic
ncp1360, ncp1365 www. onsemi.com 23 timeout the zcd block actually detects falling edges of the auxiliary winding voltage applied to the zcd pin. at start?up or during other transient phases, the zcd comparator may be unable to detect such an event. also, in the case of extremely damped oscillations, the system may not succeed in detecting all the valleys required by valley lockout operation (vlo, see next section). in this condition, the ncp1365 ensures continued operation by incorporating a maximum timeout period that resets itself when a demagnetization phase is properly detected. in case the ringing signal is too weak or heavily damped, the timeout signal supersedes the zcd signal for the valley counter. figure 50 shows the timeout period generator circuit schematic. the timeout duration, t out , is set to 5.5 s (typ.). during startup, the output voltage is still low, leading to long demagnetization phase, difficult to detect since the auxiliary winding voltage is small as well. in this condition, the t out timeout is generally shorter than the inductor demagnetization period and if used to restart a switching cycle, it can cause continuous current mode (ccm) operation for a few cycles until the voltage on the zcd pin is high enough for proper valleys detection. a longer timeout period, t outss , (typically 44 s) is therefore set during soft?start to prevent ccm operation. in vlo operation, the timeout occurrences are counted instead of valleys when the drain?source voltage oscillations are too damped to be detected. for instance, assume the circuit must turn on at the third valley and the zcd ringing only enables the detection of: ? valleys #1 to #2: the circuit generates a drv pulse t out (steady?state timeout delay) after valley #2 detection. ? valley #1: the timeout delay must run twice so that the circuit generates a drv pulse 10 s (2* t out typ.) after valley #1 detection. valley lockout (vlo) and frequency foldback (ff) the operating frequency of a traditional quasi?resonant (qr) flyback controller is inversely proportional to the system load. in other words, a load reduction increases the operating frequency. a maximum frequency clamp can be useful to limit the operating frequency range. however, when associated with a valley?switching circuit, instabilities can arise because of the discrete frequency jumps. the controller tends to hesitate between two valleys and audible noise can be generated to avoid this issue, the ncp1360/65 incorporates a proprietary valley lockout circuitry which prevents so?called valley jumping. once a valley is selected, the controller stays locked in this valley until the input level or output power changes significantly. this technique extends qr operation over a wider output power range while maintaining good efficiency and naturally limiting the maximum operating frequency. the operating valley (from 1 st to 4 th valley) is determined by the internal feedback level ( fb node on figure 4). as fb voltage level decreases or increases, the valley comparators toggle one after another to select the proper valley. the decimal counter increases each time a valley is detected. the activation of an ?n? valley comparator blanks the ?n?1? or ?n+1? valley comparator output depending if v fb decreases or increases, respectively. figure 51 shows a typical frequency characteristic obtained at low line in a 10 w charger. figure 51. typical switching frequency versus output power relationship in a 10 w adapter
ncp1360, ncp1365 www. onsemi.com 24 when an ?n? valley is asserted by the valley selection circuitry, the controller locks in this valley until the fb voltage decreases to the lower threshold (?n+1? valley activates) or increases to the ?n valley threshold? + 600 mv (?n?1? valley activates). the regulation loop adjusts the peak current to deliver the necessary output power at the valley operating point. each valley selection comparator features a 600 mv hysteresis that helps stabilize operation despite the fb voltage swing produced by the regulation loop. table 1. valley fb threshold on constant voltage regulation fb falling fb rising 1 st to 2 nd valley 2.5 v ff mode to 4 th 2.5 v 2 nd to 3 rd valley 2.3 v 4 th to 3 rd valley 2.7 v 3 rd to 4 th valley 2.1 v 3 rd to 2 nd valley 2.9 v 4 th to ff mode 1.9 v 2 nd to 1 st valley 3.1 v frequency foldback (ff) as the output current decreases ( fb voltage decreases), the valleys are incremented from 1 to 4. in case the fourth valley is reached, the fb voltage further decreases below 1.9 v and the controller enters the frequency foldback mode (ff). the current setpoint being internally forced to remain above 0.12 v (setpoint corresponding to v comp = 1.9 v), the controller regulates the power delivery by modulating the switching frequency. when an output current increase causes fb to exceed the 2.5 v ff upper threshold (600?mv hysteresis), the circuit recovers vlo operation. in frequency foldback mode, the system reduces the switching frequency by adding some dead?time after the 4 th valley is detected. however, in order to keep the high efficiency benefit inherent to the qr operation, the controller turns on again with the next valley after the dead time has ended. as a result, the controller will still run in valley switching mode even when the ff is enabled. this dead?time increases when the fb voltage decays. there is no discontinuity when the system transitions from vlo to ff and the frequency smoothly reduces as fb goes below 1.9 v . the dead?time is selected to generate a 2 s dead?time when v comp is decreasing and crossing v hvcod (1.9 v typ.). at this moment, it can linearly go down to the minimal frequency limit ( f vco(min) = 200, 600 or 1200 hz version are available). the generated dead?time is 1 s when v comp is increasing and crossing v hvcoi (2.5 v typ.). figure 52. valley lockout threshold current setpoint as explained in this operating description, the current setpoint is affected by several functions. figure 53 summarizes these interactions. as shown by this figure, the current setpoint is the output of the control law divided by k comp (4 typ.). this current setpoint is clamped by the soft?start slope as long as the peak current requested by the fb_cv or fb_cc level are higher. the softstart clamp is starting from the frozen peak current ( v cs(vco) = 120 mv typ.) to v ilim (0.8 v typ.) within 4 ms ( t ss ). however, this internal fb value is also limited by the following functions: ? a minimum setpoint is forced that equals v cs ( vco ) (0.12 v, typ.) ? in addition, a second ocp comparator ensures that in any case the current setpoint is limited to v ilim .
ncp1360, ncp1365 www. onsemi.com 25 this ensures the mosfet current setpoint remains limited to v ilim in a fault condition. fb reset max_ipk reset ocp timer count reset timer leb1 cs v ilim poreset dblehiccup leb2 v cs(stop) 4 clk counter reset counter ocp 1/k comp scp peak current freeze control law for primary peak current control softstart fb_cv fb_cc pwm latch reset pwm comp ocp comp short circuit comp r sense r cs c cs figure 53. current setpoint a 2nd over?current comparator for abnormal overcurrent fault detection a severe fault like a winding short?circuit can cause the switch current to increase very rapidly during the on?time. the current sense signal significantly exceeds v ilim . but, because the current sense signal is blanked by the leb circuit during the switch turn on, the power switch current can abnormally increase, possibly causing system damages. the ncp1360/65 protects against this dangerous mode by adding an additional comparator for abnormal overcurrent fault detection or short?circuit condition. the current sense signal is blanked with a shorter leb duration, t leb2 , typically 120 ns, before applying it to the short?circuit comparator. the voltage threshold of this extra comparator, v cs(stop) , is typically 1.2 v, set 50% higher than v ilim . this is to avoid interference with normal operation. four consecutive abnormal overcurrent faults cause the controller to enter in auto?recovery mode. the count to 4 provides noise immunity during surge testing. the counter is reset each time a drv pulse occurs without activating the fault overcurrent comparator or after double hiccup sequence or if the power supply is unplugged with a new startup sequence after the initial power on reset. standby power optimization assuming the no?load standby power is a critical parameter, the ncp1360/65 is optimized to reach an ultra low standby power. when the controller enters standby mode, a part of the internal circuitry has been disabled in order to minimize its supply current. when the stby mode is enabled, the consumption is only 200 a ( i cc4 ) with the 200 hz minimal frequency option. cable drop compensation ncp1360/65 integrates an internal cable drop compensation. this circuitry compensates the drop due to the cable connected between the pcb output of the charger and the final equipment. as the drop is linearly varying with the output current level, this level can be compensated by accounting for the load output current. figure 54 illustrates the practical implementation of the cable compensation with the ncp1360/65 controller. cc control cbc v ref_cv1 fb_cc comp ota sampled vout v ref_cv2 figure 54. cable compensation implementation
ncp1360, ncp1365 www. onsemi.com 26 the end of output cable voltage level could be written as follows: v out_cable_end (t) v out_connector (t) r cable i out (t) (eq. 13) v out_cable_end (t) v out v cbc (t) (eq. 14) v out corresponds to the nominal output level at no?load. it is independent of the output current level. then the cable compensation level could be determined as follow: v cbc (t) cbc i out (t) i out_nom (eq. 15) where: ? cbc corresponds to the cable compensation option selected (no comp, 150, 300 or 450 mv) ? i out ( t ) corresponds to the output current currently sunk by the load estimated on by the controller on the primary side. ? i out_nom the nominal output current level of the power supply. fault mode and protection ? cs pin: at each startup, a 55 a ( i cs ) current source pulls up the cs pin to disable the controller if the pin is left open or grounded. then the controller enters in a double hiccup mode. ? vs/zcd pin: after sending the first drive pulse the controller checks the correct wiring of vs/zcd pin: after the zcd blanking time, if there is an open or short conditions, the controller enters in double hiccup mode. thermal shutdown : an internal thermal shutdown circuit monitors the junction temperature of the ic. the controller is disabled if the junction temperature exceeds the thermal shutdown threshold ( t shdn ), typically 150 c. a continuous v cc hiccup is initiated after a thermal shutdown fault is detected. the controller restarts at the next v cc ( on ) once the ic temperature drops below t shdn reduced by the thermal shutdown hysteresis ( t shdn ( hys ) ) , typically 40 c. the thermal shutdown is also cleared if v cc drops below v cc ( reset ) . a new power up sequences commences at the next v cc ( on ) once all the faults are removed. driver the ncp1365 maximum supply voltage, v cc ( max ) , is 28 v. typical high?voltage mosfets have a maximum gate voltage rating of 20 v. the drv pin incorporates an active voltage clamp which limits the gate voltage on the external mosfet. the drv voltage clamp, v drv ( high ) is set to 13 v maximum. table of available options function options fault mode v cc_ovp latched / full autorecovery / v out_uvp latched cable drop compensation no/150/300/450 mv minimum operating frequency in vco 200 hz / 600 hz / 1.2 khz / 23 khz frequency clamp or maximum operating frequency no clamp / 80 khz / 110 khz ordering table option opn # ncp136_ _ _ _ y hv startup fault mode min operating fsw (stby) frequency clamp cable compensation 5 0 a b c* a b c d** e*** a b c a b c d yes no vcc_ovp latched full autorecovery vout_uvp latched 200 hz 600 hz 1.2 khz 23 khz no fmin no 80 khz 110 khz no 150 mv 300 mv 450 mv ncp1365aabcy x x x x x ncp1365babcy x x x x x ncp1365cabcy x x x x x ncp1360aabcy x x x x x ncp1360babcy x x x x x ncp1360cabcy x x x x x * available upon request ** min operating frequency d version is only available with fault mode a & b. *** min operating frequency e version is only available with fault mode c.
ncp1360, ncp1365 www. onsemi.com 27 ordering information device marking package shipping ? ncp1365aabcydr2g 1365a1 soic?7 (pb?free) 2500 / tape & reel NCP1365BABCYDR2G 1365b1 soic?7 (pb?free) 2500 / tape & reel ncp1360aabcysnt1g ada tsop?6 (pb?free) 3000 / tape & reel ncp1360babcysnt1g adc tsop?6 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1360, ncp1365 www. onsemi.com 28 package dimensions soic?7 case 751u?01 issue e seating plane 1 4 5 8 r j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b are datums and t is a datum surface. 4. dimension a and b do not include mold protrusion. 5. maximum mold protrusion 0.15 (0.006) per side. s d h c dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?a? ?b? g m b m 0.25 (0.010) ?t? b m 0.25 (0.010) t s a s m 7 pl 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches
scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncp1360, ncp1365 www. onsemi.com 29 package dimensions case 318g?02 issue u 23 4 5 6 d 1 e b e1 a1 a 0.05 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimensions d and e1 are determined at datum h. 5. pin one indicator must be located in the indicated zone. c *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max millimeters 0.90 1.00 1.10 a1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 d 2.90 3.00 3.10 e 2.50 2.75 3.00 e 0.85 0.95 1.05 l 0.20 0.40 0.60 0.25 bsc l2 ? 0 1 0 1.30 1.50 1.70 e1 e recommended note 5 l c m h l2 seating plane gauge plane detail z detail z 0.60 6x 3.20 0.95 6x 0.95 pitch dimensions: millimeters m on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1360/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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